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mos integrated circuit m m m m m pd784020, 784021 document no. u11514ej1v0ds00 (1st edition) (previous no. ip-3234) date published july 1996 p printed in japan 16/8-bit single-chip microcomputer the m pd784021 is a product of the m pd784026 sub-series in the 78k/iv series. it contains various peripheral hardware such as ram, i/o ports, 8-bit resolution a/d and d/a converters, timers, serial interface, and interrupt functions, as well as a high-speed, high-performance cpu. the m pd784021 is a rom-less product of the m pd784025 or m pd784026. the m pd784020 differs from the m pd784021 only in its ram size: 512 bytes are allocated for the m pd784020, while 2048 bytes are allocated for the m pd784021. for specific functions and other detailed information, consult the following users manual. this manual is required reading for design work. m pd784026 sub-series users manual, hardware : u10898e 78k/iv series users manual, instruction : u10905e features ? 78k/iv series ? pin-compatible with the m pd78234 sub-series ? minimum instruction execution time: 160 ns (at 25 mhz) ? number of i/o ports: 46 ? timer/counters: 16-bit timer/counter 3 units 16-bit timer 1 unit ? serial interface: 3 channels uart/ioe (3-wire serial i/o) :2 channels csi (3-wire serial i/o, sbi) : 1 channel applications lbp, automatic-focusing camera, ppc, printer, electronic typewriter, air conditioner, electronic musical instru- ments, cellular telephone, etc. this manual describes the m m m m m pd784021 unless otherwise specified. data sheet 1990 1996 ? pwm outputs: 2 ? standby function halt/stop/idle mode ? clock frequency division function ? watchdog timer : 1 channel ? a/d converter : 8-bit resolution 8 channels ? d/a converter : 8-bit resolution 2 channels ? supply voltage : v dd = 2.7 to 5.5 v the information in this document is subject to change without notice. the mark h shows major revised points.
2 m m m m m pd784020, 784021 ordering information part number package internal rom internal ram (bytes) (bytes) m pd784020gc-3b9 80-pin plastic qfp (14 14 mm) none 512 m pd784021gc-3b9 80-pin plastic qfp (14 14 mm) none 2048 m pd784021gk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm) none 2048 78k/iv series product development diagram : product under mass production : product under development : product under planning standard products development assp development h h pd784943 sub-series pd784908 sub-series m vtr servo, 100-pin, built-in analog amplifier rom: 48k/62k pd784915 sub-series m 100-pin, built-in iebus tm rom: 96k/128k m 80-pin, for cd-rom rom: 56k pd784054 80-pin, 8-bit a/d, 8-bit d/a rom: none/48k/64k m m m m m m m product containing for an i 2 c bus interface circuit 80-pin, 8-bit a/d, 8-bit d/a rom: 48k/64k/96k/128k product containing for two i 2 c bus interface circuits 100-pin, 8-bit a/d, 8-bit d/a rom: 96k/128k 80-pin, 10-bit a/d rom: 32k pd784046 sub-series sub-set pd784026 sub-series pd784216 sub-series m 80-pin, 10-bit a/d rom: 32k/64k pd784046 sub-series pd784216y sub-series pd784038 sub-series pd784038y sub-series h
3 m m m m m pd784020, 784021 functions m pd784020 m pd784021 113 8 bits 16 registers 8 banks, or 16 bits 8 registers 8 banks (memory mapping) 160 ns/320 ns/640 ns/1280 ns (at 25 mhz) none 512 bytes 2048 bytes program and data: 1m byte 46 8 34 4 32 8 8 4 bits 2, or 8 bits 1 timer/counter 0: timer register 1 pulse output capability (16 bits) capture register 1 y toggle output compare register 2 y pwm/ppg output y one-shot pulse output timer/counter 1: timer register 1 pulse output capability (8/16 bits) capture register 1 y real-time output (4 bits 2) capture/compare register 1 compare register 1 timer/counter 2: timer register 1 pulse output capability (8/16 bits) capture register 1 y toggle output capture/compare register 1 y pwm/ppg output compare register 1 timer 3 : timer register 1 (8/16 bits) compare register 1 12-bit resolution 2 channels uart/ioe (3-wire serial i/o) : 2 channels (incorporating baud rate generator) csi (3-wire serial i/o, sbi) : 1 channel 8-bit resolution 8 channels 8-bit resolution 2 channels 1 channel halt/stop/idle mode 23 (16 internal, 7 external (sampling clock variable input: 1)) + brk instruction brk instruction 1 internal, 1 external 15 internal, 6 external y 4-level programmable priority y 3 operation statuses: vectored interrupt, macro service, context switching v dd = 2.7 to 5.5 v 80-pin plastic qfp (14 14 mm) 80-pin plastic tqfp (fine pitch) (12 12 mm): for the m pd784021 only note additional function pins are included in the i/o pins. rom ram total input input/output output pins with pull- up resistor led direct drive outputs transistor direct drive h h product item number of basic instructions (mnemonics) general-purpose register minimum instruction execution time internal memory memory space i/o ports additional function pins note real-time output ports timer/counter pwm outputs serial interface a/d converter d/a converter watchdog timer standby interrupt source software nonmaskable maskable supply voltage package
4 m m m m m pd784020, 784021 contents 1. differences between m m m m m pd784026 sub-series ........................................................... 6 2. main differences between m m m m m pd784026 and m m m m m pd78234 sub-series ..................... 7 3. pin configuration (top view) ........................................................................................ 8 4. system configuration example (ppc) ....................................................................... 10 5. block diagram ..................................................................................................................... 11 6. list of pin functions ........................................................................................................ 12 6.1 port pins ...................................................................................................................................... 12 6.2 non-port pins ............................................................................................................................ 13 6.3 i/o circuits for pins and handling of unused pins ................................................. 15 7. cpu architecture .............................................................................................................. 18 7.1 memory space ........................................................................................................................... 18 7.2 cpu registers ............................................................................................................................ 21 7.2.1 general-purpose registers .......................................................................................... 21 7.2.2 control registers ........................................................................................................... 22 7.2.3 special function registers (sfrs) ............................................................................. 23 8. peripheral hardware functions ............................................................................... 28 8.1 ports ............................................................................................................................................. 28 8.2 clock generator .................................................................................................................... 29 8.3 real-time output port .......................................................................................................... 31 8.4 timers/counters ...................................................................................................................... 32 8.5 pwm output (pwm0, pwm1) ..................................................................................................... 34 8.6 a/d converter ........................................................................................................................... 35 8.7 d/a converter ........................................................................................................................... 36 8.8 serial interface ...................................................................................................................... 37 8.8.1 asynchronous serial interface/three-wire serial i/o (uart/ioe) ......................... 38 8.8.2 synchronous serial interface (csi) ............................................................................. 40 8.9 edge detection function ..................................................................................................... 41 8.10 watchdog timer ....................................................................................................................... 42 9. interrupt function ........................................................................................................... 43 9.1 interrupt source .................................................................................................................... 43 9.2 vectored interrupt ............................................................................................................... 45 9.3 context switching .................................................................................................................. 46 9.4 macro service ........................................................................................................................... 46 9.5 examples of macro service applications .................................................................. 47
5 m m m m m pd784020, 784021 10. local bus interface ......................................................................................................... 49 10.1 memory expansion .................................................................................................................. 49 10.2 memory space ........................................................................................................................... 50 10.3 programmable wait ............................................................................................................... 51 10.4 pseudo-static ram refresh function ........................................................................... 51 10.5 bus hold function .................................................................................................................. 51 11. standby function .............................................................................................................. 52 12. reset function .................................................................................................................... 53 13. instruction set ................................................................................................................... 54 14. electrical characteristics ......................................................................................... 59 15. package drawings ............................................................................................................ 80 16. recommended soldering conditions ........................................................................ 82 appendix a development tools ........................................................................................ 83 appendix b related documents ....................................................................................... 85 h h
6 m m m m m pd784020, 784021 1. differences between m m m m m pd784026 sub-series the only difference between the m pd784020, m pd784021, m pd784025, and m pd784026 is their capacity of internal memory, port functions, and part of their packages. the m pd78p4026 is produced by replacing the masked rom in the m pd784025 or m pd784026 with 64k-byte one- time prom or eprom. table 1-1 shows the differences between these products. table 1-1 differences between the m m m m m pd784026 sub-series product item internal rom internal ram p40-p47 p50-p57 p60-p63 p64, p65 package m pd784020 none 512 bytes 80-pin plastic qfp (14 14 mm) m pd784021 2048 bytes 80-pin plastic qfp (14 14 mm) 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd784025 48k bytes (masked rom) m pd784026 64k bytes (masked rom) m pd78p4026 64k bytes (one-time prom or eprom) 80-pin plastic qfp (14 14 mm) 80-pin ceramic wqfn (14 14 mm) functions only as an address/data bus functions only as an address bus can be switched to an output-only port or address bus in units of 2 bits, by using software functions only as the rd or wr pin can be switched to a general-purpose port or address/data bus, by using software can be switched to a general-purpose port or address bus in units of 2 bits, by using software functions as the rd or wr pin when the local bus interface is used. functions as a general-purpose port in other cases. 80-pin plastic qfp (14 14 mm) h
7 m m m m m pd784020, 784021 2. main differences between m m m m m pd784026 and m m m m m pd78234 sub-series series m pd784026 sub-series m pd78234 sub-series item number of basic instructions 113 65 (mnemonics) minimum instruction execution 160 ns 333 ns time (at 25 mhz) (at 12 mhz) memory space (program/data) 1m byte in total 64k bytes/1m byte timer/counter 16-bit timer/counter 1 16-bit timer/counter 1 8/16-bit timer/counter 2 8-bit timer/counter 2 8/16-bit timer 1 8-bit timer 1 clock output function available unavailable watchdog timer available unavailable serial interface uart/ioe (3-wire serial i/o) 2 channels uart 1 channel csi (3-wire serial i/o, sbi) 1 channel csi (3-wire serial i/o, sbi) 1 channel interrupt context switching available unavailable priority 4 levels 2 levels standby function 3 modes (halt, stop, idle) 2 modes (halt, stop) operation clock switching selectable from f xx /2, f xx /4, f xx /8, or f xx /16 fixed to f xx /2 pin mode pin unavailable to specify rom-less mode functions (always in the high level for the m pd78233 or m pd78237) test pin pin for testing the device unavailable low level during ordinary use package 80-pin plastic qfp (14 14 mm) 80-pin plastic qfp (14 14 mm) 80-pin plastic tqfp (fine pitch) 94-pin plastic qfp (20 20 mm) (12 12 mm): for the m pd784021 only 84-pin plastic qfj (1150 1150 mil) 80-pin ceramic wqfn (14 14 mm): 94-pin ceramic wqfn (20 20 mm): for the m pd78p4026 only for the m pd78p238 only
8 m m m m m pd784020, 784021 3. pin configuration (top view) ? 80-pin plastic qfp (14 14 mm) m pd784020gc-3b9, m pd784021gc-3b9 ? 80-pin plastic tqfp (fine pitch) (12 12 mm) m pd784021gk-be9 note connect the test pin to v ss directly. h h 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 v dd p17 p16 p15 p14/t x d2/so2 p13/r x d2/si2 p12/asck2/sck2 p11/pwm1 p10/pwm0 test note v ss astb ad0 ad1 ad2 p32/sck0 p33/so0/sb0 p34/ to0 p35/ to1 p36/ to2 p37/ to3 reset v dd x2 x1 v ss p00 p01 p02 p03 p04 p05 p06 p07 p67/refrq/hldak p66/ wait/hldrq wr rd p63/a19 p62/a18 p61/a17 p60/a16 a15 a14 a13 a12 a11 a10 a9 a8 ad7 ad6 ad5 ad4 ad3 p31/ txd/so1 p30/rxd/si1 p27/si0 p26/intp5 p25/intp4/asck/sck1 p24/intp3 p23/intp2/ci p22/intp1 p21/intp0 p20/nmi av ref3 av ref2 ano1 ano0 av ss av ref1 av dd p77/ani7 p76/ani6 p75/ani5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
9 m m m m m pd784020, 784021 p00-p07 : port 0 a8-a19 : address bus p10-p17 : port 1 rd : read strobe p20-p27 : port 2 wr : write strobe p30-p37 : port 3 wait : wait p60-p63, p66, p67 : port 6 hldrq : hold request p70-p77 : port 7 hldak : hold acknowledge to0-to3 : timer output astb : address strobe ci : clock input refrq : refresh request rxd, rxd2 : receive data reset : reset txd, txd2 : transmit data x1, x2 : crystal sck0-sck2 : serial clock ani0-ani7 : analog input asck, asck2 : asynchronous serial clock ano0, ano1 : analog output si0-si2 : serial input av ref1 -av ref3 : reference voltage so0-so2 : serial output av dd : analog power supply sb0 : serial bus av ss : analog ground pwm0, pwm1 : pulse width modulation output v dd : power supply nmi : non-maskable interrupt v ss : ground intp0-intp5 : interrupt from peripherals test : test ad0-ad7 : address/data bus
10 m m m m m pd784020, 784021 4. system configuration example (ppc) serial communication sensing paper transport temperature of the fusing heater brightness of the lamp lever for adjusting the tone of the copy lever for compensating the tone of the copy reset circuit reset ani3 ani2 ani1 ani0 intp0 txd rd oe a17 ce a8-a16 a8-a16 ad0-ad7 latch o0-o7 a0-a7 astb rxd p11 p15 p16 p17 sck1 si1 so1 p04 p06 p07 p66 pwm0 p00-p03 p33 p34 p35 p36 p37 driver sensing paper sensing paper feed sensing paper ejection sensing the position of the scanner station operator panel high-voltage control circuit fusing heater control circuit lamp regulator drum, toner, and charge for transfer fusing roller lamp for lighting the original lamp for discharging (dc stepping motor) main motor m clutch for stopping the scanner station clutch for forwarding the scanner station clutch for the resist shutter clutch for manual feeding clutch for cassette feeding solenoid sl sl sl sl sl pd784021 m pd74hc573 m pd27c1001a m
11 m m m m m pd784020, 784021 5. block diagram remark the internal rom or ram capacity differs for each product. nmi intp3 to0 to1 intp0 intp1 intp2/ci to2 to3 p00-p03 p04-p07 pwm0 pwm1 ano0 ano1 av ref2 av ref3 intp5 ani0-ani7 txd/so1 asck/sck1 rxd/si1 asck2/sck2 sck0 so0/sb0 si0 a8-a15 p00-p07 p20-p27 p10-p17 p30-p37 p60, p67 p70-p77 astb refrq/hldak wr wait/hldrq ad0-ad7 rd a16-a19 p60-p63 x1 x2 reset test v dd v ss av dd av ref1 av ss uart/ioe2 baud-rate generator uart/ioe1 clocked serial interface bus interface port 0 port 1 port 2 port 3 port 6 port 7 system control programmable interrupt controller timer/counter 0 timer/counter 1 timer/counter 2 timer 3 real-time output port pwm d /a converter a /d converter intp0-intp5 (16 bits) (16 bits) (16 bits) (16 bits) 78k /iv cpu core watchdog timer baud-rate generator txd2/so2 rxd2/si2 ram
12 m m m m m pd784020, 784021 6. list of pin functions 6.1 port pins function port 0 (p0): y 8-bit i/o port y functions as a real-time output port (4 bits 2). y inputs and outputs can be specified bit by bit. y the use of the pull-up resistors can be specified by software for the pins in the input mode together. y can drive a transistor. port 1 (p1): y 8-bit i/o port y inputs and outputs can be specified bit by bit. y the use of the pull-up resistors can be specified by software for the pins in the input mode together. y can drive led. port 2 (p2): y 8-bit input-only port y p20 does not function as a general-purpose port (nonmaskable inter- rupt). however, the input level can be checked by an interrupt service routine. y the use of the pull-up resistors can be specified by software for pins p22 to p27 (in units of 6 bits). y the p25/intp4/asck/sck1 pin functions as the sck1 output pin by csim1. port 3 (p3): y 8-bit i/o port y inputs and outputs can be specified bit by bit. y the use of the pull-up resistors can be specified by software for the pins in the input mode together. port 6 (p6): y p60 to p63 are an output-only port. y inputs and outputs can be specified bit by bit for pins p66 and p67. y the use of the pull-up resistors can be specified by software for the pins in the input mode together. port 7 (p7): y 8-bit i/o port y inputs and outputs can be specified bit by bit. i/o i/o i/o input i/o i/o i/o pin p00-p07 p10 p11 p12 p13 p14 p15-p17 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p34-p37 p60-p63 p66 p67 p70-p77 dual-function pwm0 pwm1 asck2/sck2 rxd2/si2 txd2/so2 nmi intp0 intp1 intp2/ci intp3 intp4/asck/sck1 intp5 si0 rxd/si1 txd/so1 sck0 so0/sb0 to0-to3 a16-a19 wait/hldrq refrq/hldak ani0-ani7
13 m m m m m pd784020, 784021 6.2 non-port pins (1/2) pin i/o dual-function function to0-to3 output p34-p37 timer output ci input p23/intp2 input of a count clock for timer/counter 2 r x d input p30/si1 serial data input (uart0) r x d2 p13/si2 serial data input (uart2) t x d output p31/so1 serial data output (uart0) t x d2 p14/so2 serial data output (uart2) asck input p25/intp4/sck1 baud rate clock input (uart0) asck2 p12/sck2 baud rate clock input (uart2) sb0 i/o p33/so0 serial data i/o (sbi) si0 input p27 serial data input (3-wire serial i/o0) si1 p30/r x d serial data input (3-wire serial i/o1) si2 p13/r x d2 serial data input (3-wire serial i/o2) so0 output p33/sb0 serial data output (3-wire serial i/o0) so1 p31/t x d serial data output (3-wire serial i/o1) so2 p14/t x d2 serial data output (3-wire serial i/o2) sck0 i/o p32 serial clock i/o (3-wire serial i/o0, sbi) sck1 p25/intp4/asck serial clock i/o (3-wire serial i/o1) sck2 p12/asck2 serial clock i/o (3-wire serial i/o2) nmi input p20 external interrupt request intp0 p21 y input of a count clock for timer/counter 1 y capture/trigger signal for cr11 or cr12 intp1 p22 y input of a count clock for timer/counter 2 y capture/trigger signal for cr22 intp2 p23/ci y input of a count clock for timer/counter 2 y capture/trigger signal for cr21 intp3 p24 y input of a count clock for timer/counter 0 y capture/trigger signal for cr02 intp4 p25/asck/sck1 intp5 p26 input of a conversion start trigger for a/d converter ad0-ad7 i/o time multiplexing address/data bus (for connecting external memory) a8-a15 output high-order address bus (for connecting external memory) a16-a19 output p60-p63 high-order address bus during address expansion (for connecting external memory) rd output strobe signal output for reading the contents of external memory wr output strobe signal output for writing on external memory wait input p66/hldrq wait signal insertion refrq output p67/hldak refresh pulse output to external pseudo static memory hldrq input p66/wait input of bus hold request hldak output p67/refrq output of bus hold response astb output latch timing output of time multiplexing address (a0-a7) (for connecting external memory)
14 m m m m m pd784020, 784021 6.2 non-port pins (2/2) pin i/o dual-function function reset input chip reset x1 input crystal input for system clock oscillation (a clock pulse can also be x2 input to the x1 pin.) ani0-ani7 input p70-p77 analog voltage inputs for the a/d converter ano0, ano1 output analog voltage inputs for the d/a converter av ref1 application of a/d converter reference voltage av ref2 , av ref3 application of d/a converter reference voltage av dd positive power supply for the a/d converter av ss ground for the a/d converter v dd positive power supply v ss ground test directly connect to v ss . (the test pin is for the ic test.)
15 m m m m m pd784020, 784021 6.3 i/o circuits for pins and handling of unused pins table 6-1 describes the types of i/o circuits for pins and the handling of unused pins. fig. 6-1 shows the configuration of these various types of i/o circuits. table 6-1 types of i/o circuits for pins and handling of unused pins (1/2) note these pins function as output-only pins depending on the internal circuit, though their i/o type is 5-a. pin i/o circuit type i/o recommended connection method for unused pins p00-p07 5-a i/o input state : to be connected to v dd p10/pwm0 output state: to be left open p11/pwm1 p12/asck2/sck2 8-a p13/rxd2/si2 5-a p14/txd2/so2 p15-p17 p20/nmi 2 input to be connected to v dd or v ss p21/intp0 p22/intp1 2-a to be connected to v dd p23/intp2/ci p24/intp3 p25/intp4/asck/sck1 8-a i/o input state : to be connected to v dd output state: to be left open p26/intp5 2-a input to be connected to v dd p27/si0 p30/rxd/si1 5-a i/o input state : to be connected to v dd p31/txd/so1 output state: to be left open p32/sck0 8-a p33/so0/sb0 10-a p34/to0-p37/to3 5-a ad0-ad7 a8-a15 output note to be left open p60/a16-p63/a19 rd wr p66/wait/hldrq i/o input state : to be connected to v dd p67/refrq/hldak output state: to be left open p70/ani0-p77/ani7 20 input state : to be connected to v dd or v ss output state: to be left open ano0, ano1 12 output to be left open astb 4
16 m m m m m pd784020, 784021 table 6-1 types of i/o circuits for pins and handling of unused pins (2/2) pin i/o circuit type i/o recommended connection method for unused pins reset 2 input test 1 to be connected to v ss directly av ref1 -av ref3 to be connected to v ss av ss av dd to be connected to v dd caution when the i/o mode of an i/o dual-function pin is unpredictable, connect the pin to v dd through a resistor of 10 to 100 kilohms (particularly when the voltage of the reset input pin becomes higher than that of the low level input at power-on or when i/o is switched by software). remark since type numbers are consistent in the 78k series, those numbers are not always serial in each product. (some circuits are not included.)
17 m m m m m pd784020, 784021 fig. 6-1 i/o circuits for pins type 1 type 2-a type 2 type 4 type 8-a type 10-a type 5-a type 12 type 20 in schmitt trigger input with hysteresis characteristics schmitt trigger input with hysteresis characteristics in v dd p pull-up enable in v dd p n data v dd p n out output disable push-pull output which can output high impedance (both the positive and negative channels are off.) data v dd p n in/out output disable v dd p pull-up enable input enable data v dd p n in/out output disable v dd p pull-up enable data v dd p n in/out output disable v dd p pull-up enable open drain n p analog output voltage out data comparator v dd v ref p (threshold voltage) p n n in/out output disable input enable +
18 m m m m m pd784020, 784021 7. cpu architecture 7.1 memory space a 1m-byte memory space can be accessed. by using a location instruction, the mode for mapping internal data areas (special function registers and internal ram) can be selected. a location instruction must always be executed after a reset, and can be used only once. (1) when the location 0 instruction is executed internal data areas are mapped to 0fd00h-0ffffh for the m pd784020 and 0f700h-0ffffh for the m pd784021. (2) when the location 0fh instruction is executed internal data areas are mapped to ffd00h-fffffh for the m pd784020 and ff700h-fffffh for the m pd784021.
19 m m m m m pd784020, 784021 fig. 7-1 m m m m m pd784020 memory map h h h h h note base area, or entry area based on a reset or interrupt. internal ram is excluded in the case of a reset. internal ram (512 bytes) external memory (960k bytes) general-purpose registers (128 bytes) macro service control word area (42 bytes) callf entry area (2k bytes) callt table area (64 bytes) vector table area (64 bytes) internal ram (512 bytes) external memory (1,047,808 bytes) when the location 0 instruction is executed special function registers (sfrs) (256 bytes) data area (512 bytes) when the location 0fh instruction is executed special function registers (sfrs) (256 bytes) external memory (64,768 bytes) note note fffffh 10000h 0ffffh 0ffdfh 0ffd0h 0ff00h 0feffh 0fd00h 0fcffh 00000h 0feffh 0fe80h 0fe7fh 0fe2fh 0fe06h 0fd00h 00fffh 00800h 007ffh 00080h 0007fh 00040h 0003fh 00000h ffeffh ffe80h ffe7fh ffe2fh ffe06h ffd00h 00fffh 00800h 007ffh 00080h 0007fh fffffh fffdfh fffd0h fff00h ffeffh ffd00h ffcffh 10000h 0ffffh 00000h
20 m m m m m pd784020, 784021 fig. 7-2 m m m m m pd784021 memory map note base area, or entry area based on a reset or interrupt. internal ram is excluded in the case of a reset. internal ram (2,048 bytes) external memory (960k bytes) general-purpose registers (128 bytes) macro service control word area (42 bytes) program/data area (1,536 bytes) callf entry area (2k bytes) callt table area (64 bytes) vector table area (64 bytes) internal ram (2,048 bytes) external memory (1,046,272 bytes) when the location 0 instruction is executed special function registers (sfrs) (256 bytes) data area (512 bytes) when the location 0fh instruction is executed special function registers (sfrs) (256 bytes) external memory (63,232 bytes) note note fffffh 10000h 0ffffh 0ffdfh 0ffd0h 0ff00h 0feffh 0fd00h 0fcffh 0f700h 0f6ffh 00000h 0feffh 0fe80h 0fe7fh 0fe2fh 0fe06h 0fd00h 0fcffh 0f700h 00fffh 00800h 007ffh 00080h 0007fh 00040h 0003fh 00000h ffeffh ffe80h ffe7fh ffe2fh ffe06h ffd00h ffcffh ff700h 00fffh 00800h 007ffh 00080h 0007fh fffffh fffdfh fffd0h fff00h ffeffh ff700h ff6ffh 10000h 0ffffh 00000h
21 m m m m m pd784020, 784021 7.2 cpu registers 7.2.1 general-purpose registers a set of general-purpose registers consists of sixteen general-purpose 8-bit registers. two 8-bit general-purpose registers can be combined to form a 16-bit general-purpose register. moreover, four 16-bit general-purpose registers, when combined with an 8-bit register for address extension, can be used as 24-bit address specification registers. eight banks of this register set are provided. the user can switch between banks by software or the context switching function. general-purpose registers other than the v, u, t, and w registers used for address extension are mapped onto internal ram. fig. 7-3 general-purpose register format caution by setting the rss bit of psw to 1, r4, r5, r6, r7, rp2, and rp3 can be used as the x, a, c, b, ax, and bc registers, respectively. however, this function must be used only when using programs for the 78k/iii series. a (r1) x (r0) b (r3) c (r2) r5 r4 r7 r6 r9 r8 r11 r10 d (r13) e (r12) h (r15) v u t w l (r14) ax (rp0) bc (rp1) rp2 rp3 vp (rp4) up (rp5) de (rp6) hl (rp7) vvp (rg4) uup (rg5) tde (rg6) whl (rg7) the character strings enclosed in parentheses represent absolute names. 8 banks
22 m m m m m pd784020, 784021 7.2.2 control registers (1) program counter (pc) this register is a 20-bit program counter. the program counter is automatically updated by program execution. fig. 7-4 format of program counter (pc) (2) program status word (psw) this register holds the cpu state. the program status word is automatically updated by program execution. fig. 7-5 format of program status word (psw) note this flag is used to maintain compatibility with the 78k/iii series. this flag must be set to 0 when programs for the 78k/iii series are being used. (3) stack pointer (sp) this register is a 24-bit pointer for holding the start address of the stack. the high-order 4 bits must be set to 0. fig. 7-6 format of stack pointer (sp) 19 0 pc pswh pswl psw 15 14 13 12 uf rbs2 rbs1 rbs0 11 10 9 8 76543210 s z rss note ac ie p/v 0 cy 23 20 0 pc 0 0 0 0
23 m m m m m pd784020, 784021 7.2.3 special function registers (sfrs) the special function registers are registers with special functions such as mode registers and control registers for built-in peripheral hardware. the special function registers are mapped onto the 256-byte space between 0ff00h and 0ffffh note . note applicable when the location 0 instruction is executed. fff00h-fffffh when the location 0fh instruction is executed. caution never attempt to access addresses in this area where no sfr is allocated. otherwise, the m m m m m pd784021 may be placed in the deadlock state. the deadlock state can be cleared only by a reset. table 7-1 lists the special function registers (sfrs). the titles of the table columns are explained below. ? abbreviation ................... symbol used to represent a built-in sfr. the abbreviations listed in the table are reserved words for the nec assembler (ra78k4). the c compiler (cc78k4) allows the abbreviations to be used as sfr variables of bit type with the #pragma sfr command. ? r/w ................................. indicates whether each sfr allows read and/or write operations. r/w : allows both read and write operations. r : allows read operations only. w : allows write operations only. ? manipulatable bits .......... indicates the maximum number of bits that can be manipulated whenever an sfr is manipulated. an sfr that supports 16-bit manipulation can be described in the sfr operand. for address specification, an even-numbered address must be speci- fied. an sfr that supports 1-bit manipulation can be described in a bit manipulation instruction. ? when reset ..................... indicates the state of each register when reset is applied. h
24 m m m m m pd784020, 784021 table 7-1 special function registers (sfrs) (1/4) address note special function register (sfr) name abbreviation r/w manipulatable bits when reset 1 bit 8 bits 16 bits 0ff00h port 0 p0 r/w ll C undefined 0ff01h port 1 p1 ll C 0ff02h port 2 p2 r ll C 0ff03h port 3 p3 r/w ll C 0ff06h port 6 p6 ll C 00h 0ff07h port 7 p7 ll C undefined 0ff0eh port 0 buffer register l p0l ll C 0ff0fh port 0 buffer register h p0h ll C 0ff10h compare register (timer/counter 0) cr00 C C l 0ff12h capture/compare register (timer/counter 0) cr01 C C l 0ff14h compare register l (timer/counter 1) cr10 cr10w C ll 0ff15h compare register h (timer/counter 1) C C C 0ff16h capture/compare register l (timer/counter 1) cr11 cr11w C ll 0ff17h capture/compare register h (timer/counter 1) C C C 0ff18h compare register l (timer/counter 2) cr20 cr20w C ll 0ff19h compare register h (timer/counter 2) C C C 0ff1ah capture/compare register l (timer/counter 2) cr21 cr21w C ll 0ff1bh capture/compare register h (timer/counter 2) C C C 0ff1ch compare register l (timer 3) cr30 cr30w C ll 0ff1dh compare register h (timer 3) C C C 0ff20h port 0 mode register pm0 ll C ffh 0ff21h port 1 mode register pm1 ll C 0ff23h port 3 mode register pm3 ll C 0ff26h port 6 mode register pm6 ll C 0ff27h port 7 mode register pm7 ll C 0ff2eh real-time output port control register rtpc ll C 00h 0ff30h capture/compare control register 0 crc0 C l C 10h 0ff31h timer output control register toc ll C 00h 0ff32h capture/compare control register 1 crc1 C l C 0ff33h capture/compare control register 2 crc2 C l C 10h note applicable when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to each address.
25 m m m m m pd784020, 784021 table 7-1 special function registers (sfrs) (2/4) address note special function register (sfr) name abbreviation r/w manipulatable bits when reset 1 bit 8 bits 16 bits 0ff36h capture register (timer/counter 0) cr02 r C C l 0000h 0ff38h capture register l (timer/counter 1) cr12 cr12w C ll 0ff39h capture register h (timer/counter 1) C C C 0ff3ah capture register l (timer/counter 2) cr22 cr22w C ll 0ff3bh capture register h (timer/counter 2) C C C 0ff41h port 1 mode control register pmc1 r/w ll C 00h 0ff43h port 3 mode control register pmc3 ll C 0ff4eh register for optional pull-up resistor puo ll C 0ff50h timer register 0 tm0 r C C l 0000h 0ff51h CC 0ff52h timer register 1 tm1 tm1w C ll 0ff53h C C C 0ff54h timer register 2 tm2 tm2w C ll 0ff55h C C C 0ff56h timer register 3 tm3 tm3w C ll 0ff57h C C C 0ff5ch prescaler mode register 0 prm0 r/w C l C 11h 0ff5dh timer control register 0 tmc0 ll C 00h 0ff5eh prescaler mode register 1 prm1 C l C 11h 0ff5fh timer control register 1 tmc1 ll C 00h 0ff60h d/a conversion value setting register 0 dacs0 C l C 0ff61h d/a conversion value setting register 1 dacs1 C l C 0ff62h d/a converter mode register dam ll C 03h 0ff68h a/d converter mode register adm ll C 00h 0ff6ah a/d conversion result register adcr r C l C undefined 0ff70h pwm control register pwmc r/w ll C 05h 0ff71h pwm prescaler register pwpr C l C 00h 0ff72h pwm modulo register 0 pwm0 C C l undefined 0ff74h pwm modulo register 1 pwm1 C C l 0ff7dh one-shot pulse output control register ospc ll C 00h 0ff80h serial bus interface control register sbic ll C 0ff82h synchronous serial interface mode register csim ll C note applicable when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to each address.
26 m m m m m pd784020, 784021 address note 1 special function register (sfr) name abbreviation r/w manipulatable bits when reset 1 bit 8 bits 16 bits 0ff84h synchronous serial interface mode register 1 csim1 r/w ll C 00h 0ff85h synchronous serial interface mode register 2 csim2 ll C 0ff86h serial shift register sio C l C 0ff88h asynchronous serial interface mode register asim ll C 0ff89h asynchronous serial interface mode register 2 asim2 ll C 0ff8ah asynchronous serial interface status register asis r ll C 0ff8bh asynchronous serial interface status register 2 asis2 ll C 0ff8ch serial receive buffer: uart0 rxb C l C undefined serial transmission shift register: uart0 txs w C l C serial shift register: ioe1 sio1 r/w C l C 0ff8dh serial receive buffer: uart2 rxb2 r C l C serial transmission shift register: uart2 txs2 w C l C serial shift register: ioe2 sio2 r/w C l C 0ff90h baud rate generator control register brgc C l C 00h 0ff91h baud rate generator control register 2 brgc2 C l C 0ffa0h external interrupt mode register 0 intm0 ll C 0ffa1h external interrupt mode register 1 intm1 ll C 0ffa4h sampling clock selection register scs0 C l C 0ffa8h in-service priority register ispr r ll C 0ffaah interrupt mode control register imc r/w ll C 80h 0ffach interrupt mask register 0l mk0l mk0 lll ffffh 0ffadh interrupt mask register 0h mk0h ll 0ffaeh interrupt mask register 1l mk1l ll C ffh 0ffc0h standby control register stbc C l note 2 C 30h 0ffc2h watchdog timer mode register wdm C l note 2 C 00h 0ffc4h memory expansion mode register mm ll C 20h 0ffc5h hold mode register hldm ll C 00h 0ffc6h clock output mode register clom ll C 0ffc7h programmable wait control register 1 pwc1 C l C aah 0ffc8h programmable wait control register 2 pwc2 C C l aaaah table 7-1 special function registers (sfrs) (3/4) notes 1. applicable when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to each address. 2. a write operation can be performed only with special instructions mov stbc,#byte and mov wdm,#byte. other instructions cannot perform a write operation.
27 m m m m m pd784020, 784021 table 7-1 special function registers (sfrs) (4/4) note applicable when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to each address. address note special function register (sfr) name abbreviation r/w manipulatable bits when reset 1 bit 8 bits 16 bits 0ffcch refresh mode register rfm r/w ll C 00h 0ffcdh refresh area specification register rfa ll C 0ffcfh oscillation settling time specification register osts C l C 0ffd0h- external sfr area C ll C C 0ffdfh 0ffe0h interrupt control register (intp0) pic0 ll C 43h 0ffe1h interrupt control register (intp1) pic1 ll C 0ffe2h interrupt control register (intp2) pic2 ll C 0ffe3h interrupt control register (intp3) pic3 ll C 0ffe4h interrupt control register (intc00) cic00 ll C 0ffe5h interrupt control register (intc01) cic01 ll C 0ffe6h interrupt control register (intc10) cic10 ll C 0ffe7h interrupt control register (intc11) cic11 ll C 0ffe8h interrupt control register (intc20) cic20 ll C 0ffe9h interrupt control register (intc21) cic21 ll C 0ffeah interrupt control register (intc30) cic30 ll C 0ffebh interrupt control register (intp4) pic4 ll C 0ffech interrupt control register (intp5) pic5 ll C 0ffedh interrupt control register (intad) adic ll C 0ffeeh interrupt control register (intser) seric ll C 0ffefh interrupt control register (intsr) sric ll C interrupt control register (intcsi1) csiic1 ll C 0fff0h interrupt control register (intst) stic ll C 0fff1h interrupt control register (intcsi) csiic ll C 0fff2h interrupt control register (intser2) seric2 ll C 0fff3h interrupt control register (intsr2) sric2 ll C interrupt control register (intcsi2) csiic2 ll C 0fff4h interrupt control register (intst2) stic2 ll C
28 m m m m m pd784020, 784021 8. peripheral hardware functions 8.1 ports the ports shown in fig. 8-1 are provided to enable the application of wide-ranging control. table 8-1 lists the functions of the ports. for the inputs to port 0 to port 6, a built-in pull-up resistor can be specified by software. fig. 8-1 port configuration port 0 p00 p07 8 port 1 p10 p17 port 2 p20-p27 port 3 p30 p37 port 6 p60 p63 p66 p67 port 7 p70 p77
29 m m m m m pd784020, 784021 table 8-1 port functions 8.2 clock generator a circuit for generating the clock signal required for operation is provided. the clock generator includes a frequency divider; low current consumption can be achieved by operating at a lower internal frequency when high-speed operation is not necessary. fig. 8-2 block diagram of clock generator remark f xx : oscillator frequency or external clock input f clk : internal operating frequency port name pin function pull-up specification by software port 0 p00-p07 ? bit-by-bit input/output setting supported specified as a batch for all pins placed in ? operable as 4-bit real-time outputs input mode. (p00-p03, p04-p07) ? capable of driving transistors port 1 p10-p17 ? bit-by-bit input/output setting supported specified as a batch for all pins placed in ? capable of driving leds input mode. port 2 p20-p27 ? input port specified for the 6 bits (p22-p27) as a batch. port 3 p30-p37 ? bit-by-bit input/output setting supported specified as a batch for all pins placed in input mode. port 6 p60-p63 ? output-only port p66, p67 ? bit-by-bit input/output setting supported port 7 p70-p77 ? bit-by-bit input/output setting supported specified as a batch for all pins placed in input mode. x1 x2 f xx /2 f xx f clk cpu peripheral circuits oscillator uart/ioe intp0 noise eliminator oscillation settling timer selector 1/2 1/2 1/2 1/2
30 m m m m m pd784020, 784021 fig. 8-3 examples of using oscillator (1) crystal/ceramic oscillation (2) external clock ? when extc bit of osts = 1 ? when extc bit of osts = 0 caution when using the clock generator, to avoid problems caused by influences such as stray capacitance, run all wiring within the area indicated by the dotted lines according to the following rules: ? minimize the wiring length. ? wires must never cross other signal lines. ? wires must never run near a line carrying a large varying current. ? the grounding point of the capacitor of the oscillator circuit must always be at the same potential as v ss . never connect the capacitor to a ground pattern carrying a large current. ? never extract a signal from the oscillator circuit. v ss x1 x2 pd784021 m pd784021 x1 x2 pd74hc04, etc. m m x1 x2 open pd784021 m h
31 m m m m m pd784020, 784021 8.3 real-time output port the real-time output port outputs data stored in the buffer, synchronized with a timer/counter 1 match interrupt or external interrupt. thus, pulse output that is free of jitter can be obtained. therefore, the real-time output port is best suited to applications (such as open-loop control over stepping motors) where an arbitrary pattern is output at arbitrary intervals. as shown in fig. 8-4, the real-time output port is built around port 0 and the port 0 buffer register (p0h, p0l). fig. 8-4 block diagram of real-time output port 4 4 4 p0l p0h buffer register 8 4 8 p00 p07 output latch (p0) real-time output port control register (rtpc) output trigger control circuit intp0 (externally) intc10 (from timer/counter 1) intc11 (from timer/counter 1) internal bus
32 m m m m m pd784020, 784021 name timer/counter 0 timer/counter 1 timer/counter 2 timer 3 item count pulse width 8 bits C lll 16 bits llll operating mode interval timer 2ch 2ch 2ch 1ch external event counter lll C one-shot timer C C l C function timer output 2ch C 2ch C toggle output l C l C pwm/ppg output l C l C one-shot pulse output note l CCC real-time output C l CC pulse width measurement 1 input 1 input 2 inputs C number of interrupt requests 2 2 2 1 8.4 timers/counters three timer/counter units and one timer unit are incorporated. moreover, seven interrupt requests are supported, allowing these units to function as seven timer/counter units. table 8-2 timer/counter operation note the one-shot pulse output function makes the level of a pulse output active by software, and makes the level of a pulse output inactive by hardware (interrupt request signal). note that this function differs from the one-shot timer function of timer/counter 2. h
33 m m m m m pd784020, 784021 fig. 8-5 timer/counter block diagram timer/counter 0 timer/counter 1 timer/counter 2 timer 3 remark ovf: overflow flag to1 f xx /8 ovf to0 intp3 intp3 intc00 intc01 clear information prescaler selector timer register 0 (tm0) software trigger compare register (cr00) match match pulse output control compare register (cr01) edge detection capture register (cr02) to3 f xx /8 ovf to2 intp1 intp1 intc20 intc21 intp2/c1 intp2 clear information prescaler selector timer register 2 (tm2/tm2w) edge detection edge detection compare register (cr20/cr20w) match match capture/compare register (cr21/cr21w) pulse output control capture register (cr22/cr22w) f xx /8 timer register 3 (tm3/tm3w) compare register (cr30/cr30w) prescaler csi clear match intc30 h f xx /8 ovf intp0 intp0 intc10 intc11 clear information prescaler selector timer register 1 (tm1/tm1m) event input compare register (cr10/cr10w) match match edge detection capture/compare register (cr11/cr11w) to real-time output port capture register (cr12/cr12w)
34 m m m m m pd784020, 784021 8.5 pwm output (pwm0, pwm1) two channels of pwm (pulse width modulation) output circuitry with a resolution of 12 bits and a repetition frequency of 48.8 khz (f clk = 12.5 mhz) are incorporated. low or high active level can be selected for the pwm output channels, independently of each other. this output is best suited to dc motor speed control. fig. 8-6 block diagram of pwm output unit remark n = 0, 1 internal bus pwm modulo register pwm control register (pwmc) reload control prescaler 8-bit down-counter pulse control circuit 4-bit counter output control pwmn (output pin) 1/256 f clk 84 16 8 pwmn 15 0 8 7 4 3
35 m m m m m pd784020, 784021 8.6 a/d converter an analog/digital (a/d) converter having 8 multiplexed analog inputs (ani0-ani7) is incorporated. the successive approximation system is used for conversion. the result of conversion is held in the 8-bit a/d conversion result register (adcr). thus, speedy high-precision conversion can be achieved. (the conversion time is about 10 m s at f clk = 12.5 mhz.) a/d conversion can be started in any of the following modes: ? hardware start : conversion is started by means of trigger input (intp5). ? software start : conversion is started by means of bit setting the a/d converter mode register (adm). after conversion has started, one of the following modes can be selected: ? scan mode : multiple analog inputs are selected sequentially to obtain conversion data from all pins. ? select mode: a single analog input is selected at all times to enable conversion data to be obtained continuously. adm is used to specify the above modes, as well as the termination of conversion. when the result of conversion is transferred to adcr, an interrupt request (intad) is generated. using this feature, the results of conversion can be continuously transferred to memory by the macro service. fig. 8-7 block diagram of a/d converter ani0 ani7 intp5 av ref1 av ss r/2 r r/2 8 8 8 input selector tap selector sample-and-hold circuit voltage comparator successive conver- sion register (sar) series resistor string control circuit a/ d converter mode register (adm) a/ d conversion result register (adcr) internal bus edge detector conversion trigger trigger enable intad ani1 ani2 ani3 ani4 ani5 ani6
36 m m m m m pd784020, 784021 8.7 d/a converter two digital/analog (d/a) converter channels of voltage output type, having a resolution of 8 bits, are incorporated. a resistor string system is used for conversion. by writing the value to be subject to d/a conversion in the 8-bit d/a conversion value setting register (dacsn: n = 0, 1), the resulting analog value is output on anon (n = 0, 1). the range of the output voltages is determined by the voltages applied to the av ref2 and av ref3 pins. because of its high output impedance, no current can be obtained from an output pin. when the load impedance is low, insert a buffer amplifier between the load and the converter. the impedance of the anon pin goes high while the reset signal is low. dacsn is set to 0 after a reset is released. fig. 8-8 block diagram of d/a converter remark n = 0, 1 8 av ref2 r r r r av ref3 anon dacen 8 dacsn reset tap selector internal bus
37 m m m m m pd784020, 784021 8.8 serial interface three independent serial interface channels are incorporated. ? asynchronous serial interface (uart)/three-wire serial i/o (ioe) 2 ? synchronous serial interface (csi) 1 ? three-wire serial i/o (ioe) ? serial bus interface (sbi) so, communication with points external to the system and local communication within the system can be performed at the same time. (see fig. 8-9 .) fig. 8-9 example serial interfaces note handshake line sb0 sck (a) uart + sbi rs-232-c driver/ receiver port rxd txd sb0 sck0 pd75402a (slave) m pd75328 (slave) m pd784021 (master) m pd4711a m v dd sb0 lcd sck (uart) (sbi) port rxd2 txd2 pd4711a m (uart) rs-232-c driver/ receiver si so sck port int (b) uart + three-wire serial i/o [three-wire serial i/o] rs-232-c driver/ receiver port rxd txd so0 si0 sck0 intpm port so1 si1 intpn sck1 port note pd75108 (slave) m pd784021 (master) m pd4711a m si so sck port int note pd78014 (slave) m (uart)
38 m m m m m pd784020, 784021 8.8.1 asynchronous serial interface/three-wire serial i/o (uart/ioe) two serial interface channels are available; for each channel, asynchronous serial interface mode or three-wire serial i/o mode can be selected. (1) asynchronous serial interface mode in this mode, 1-byte data is transferred after a start bit. a baud rate generator is incorporated to enable communication at a wide range of baud rates. moreover, the frequency of a clock signal applied to the asck pin can be divided to define a baud rate. with the baud rate generator, the baud rate conforming to the midi standard (31.25 kbps) can be obtained. fig. 8-10 block diagram of asynchronous serial interface mode remark f xx : oscillator frequency or external clock input n = 0 to 11 m = 16 to 30 rxb, rxb2 txs, txs2 intst, intst2 intsr, intsr2 intser, intser2 1/2m f xx /2 asck, asck2 txd, txd2 rxd, rxd2 1/2 n+1 1/2m baud rate generator receive shift register receive buffer selector transmission control parity bit addition transmission shift register internal bus reception control parity check
39 m m m m m pd784020, 784021 (2) three-wire serial i/o mode in this mode, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock. this mode is designed for communication with a device incorporating a conventional synchronous serial interface. basically, three lines are used for communication: the serial clock line (sck) and the two serial data lines (si and so). in general, a handshake line is required to check the state of communication. fig. 8-11 block diagram of three-wire serial i/o mode remark f xx : oscillator frequency or external clock input n = 0 to 11 m = 1, 16 to 30 serial clock counter sio1, sio2 si1, si2 so1, so2 sck1, sck2 f xx /2 intcsi1, intcsi2 shift register output latch direction control circuit internal bus serial clock control circuit selector 1/m 1/2 n+1 interrupt signal generator
40 m m m m m pd784020, 784021 8.8.2 synchronous serial interface (csi) with this interface, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock. fig. 8-12 block diagram of synchronous serial interface remark f clk : internal system clock frequency (system clock frequency/2) direction control circuit selector shift register set clear output latch serial clock counter serial clock control circuit selector tm 3 output/2 f clk /8 f clk /32 intcsi sck0 si0 so0/sb0 internal bus interrupt signal generation circuit busy/ acknowledge detection circuit bus release/ command/ acknowledge detection circuit sio n-ch open-drain output enabled (when sb0 or sbi mode is used)
41 m m m m m pd784020, 784021 (1) three-wire serial i/o mode this mode is designed for communication with a device incorporating a conventional synchronous serial interface. basically, three lines are used for communication: the serial clock line (sck0) and serial data lines (si0 and so0). in general, a handshake line is required to check the state of communication. (2) sbi mode the sbi mode allows communication with more than one device via two lines: the serial clock (sck0) and serial bus (sb0). the sbi mode is the standard nec serial interface. a master device outputs an address through the sb0 pin to select a slave device with which communication is to be performed. after a target device is selected, commands and data are transmitted between the master device and slave device. 8.9 edge detection function the interrupt input pins (nmi, intp0-intp5) are used to apply not only interrupt requests but also trigger signals for the built-in circuits. as these pins are triggered by an edge (rising or falling) of an input signal, a function for edge detection is incorporated. moreover, a noise suppression function is provided to prevent erroneous edge detection caused by noise. note intp0 is used for sampling clock selection. pin detectable edge noise suppression method nmi rising edge or falling edge analog delay intp0-intp3 rising edge or falling edge, or both edges clock sampling note intp4, intp5 analog delay
42 m m m m m pd784020, 784021 8.10 watchdog timer a watchdog timer is incorporated for cpu runaway detection. the watchdog timer, if not cleared by software within a specified interval, generates a nonmaskable interrupt. furthermore, once watchdog timer operation is enabled, it cannot be disabled by software. the user can specify whether priority is placed on an interrupt based on the watchdog timer or on an interrupt based on the nmi pin. fig. 8-13 block diagram of watchdog timer f clk /2 21 f clk intwdt f clk /2 20 f clk /2 19 f clk /2 17 timer clear signal selector h
43 m m m m m pd784020, 784021 9. interrupt function table 9-1 lists the interrupt request handling modes. these modes are selected by software. table 9-1 interrupt request handling modes 9.1 interrupt source an interrupt can be issued from any one of the interrupt sources listed in table 9-2: execution of a brk instruction, an operand error, or any of the 23 other interrupt sources. four levels of interrupt handling priority can be set. priority levels can be set to nest control during interrupt handling or to concurrently generate interrupt requests. nested macro services, however, are performed without suspension. when interrupt requests having the same priority level are generated, they are handled according to the default priority (fixed). (see table 9-2 .) handling mode handled by handling pc and psw contents vectored interrupt software branches to a handling routine for execution the pc and psw contents are pushed (arbitrary handling). to and popped from the stack. context switching automatically selects a register bank, and the pc and psw contents are saved to branches to a handling routine for execution and read from a fixed area in the (arbitrary handling). register bank. macro service firmware performs operations such as memory-to-i/o- maintained device data transfer (fixed handling).
44 m m m m m pd784020, 784021 table 9-2 interrupt sources remark asi: asynchronous serial interface csi: synchronous serial interface h type default source internal/ macro priority name trigger external service software C brk instruction instruction execution C C operand error when the mov stbc,#byte or mov wdm,#byte instruction is executed, exclusive or of the byte operand and byte does not produce ffh. nonmaskable C nmi detection of edge input on the pin external C wdt watchdog timer overflow internal maskable 0 (highest) intp0 detection of edge input on the pin (tm1/tm1w capture trigger) external enabled 1 intp1 detection of edge input on the pin (tm2/tm2w capture trigger) 2 intp2 detection of edge input on the pin (tm2/tm2w event counter input) 3 intp3 detection of edge input on the pin (tm0 capture trigger) 4 intc00 tm0-cr00 match signal issued internal enabled 5 intc01 tm0-cr01 match signal issued 6 intc10 tm1-cr10 match signal issued (in 8-bit operation mode) tm1w-cr10w match signal issued (in 16-bit operation mode) 7 intc11 tm1-cr11 match signal issued (in 8-bit operation mode) tm1w-cr11w match signal issued (in 16-bit operation mode) 8 intc20 tm2-cr20 match signal issued (in 8-bit operation mode) tm2w-cr20w match signal issued (in 16-bit operation mode) 9 intc21 tm2-cr21 match signal issued (in 8-bit operation mode) tm2w-cr21w match signal issued (in 16-bit operation mode) 10 intc30 tm3-cr30 match signal issued (in 8-bit operation mode) tm3w-cr30w match signal issued (in 16-bit operation mode) 11 intp4 detection of edge input on the pin external enabled 12 intp5 detection of edge input on the pin 13 intad a/d converter processing completed (adcr transfer) internal enabled 14 intser asi0 reception error C 15 intsr asi0 reception completed or csi1 transfer completed enabled intcsi1 16 intst asi0 transmission completed 17 intcsi csi0 transfer completed 18 intser2 asi2 reception error C 19 intsr2 asi2 reception completed or csi2 transfer completed enabled intcsi2 20 (lowest) intst2 asi2 transmission completed
45 m m m m m pd784020, 784021 9.2 vectored interrupt when a branch to an interrupt handling routine occurs, the vector table address corresponding to the interrupt source is used as the branch address. interrupt handling by the cpu consists of the following operations : ? when a branch occurs : push the cpu status (pc and psw contents) to the stack. ? when control is returned: pop the cpu status (pc and psw contents) from the stack. to return control from the handling routine to the main routine, use the reti instruction. the branch destination addresses must be within the range of 0 to ffffh. table 9-3 vector table address interrupt source vector table address brk instruction 003eh operand error 003ch nmi 0002h wdt 0004h intp0 0006h intp1 0008h intp2 000ah intp3 000ch intc00 000eh intc01 0010h intc10 0012h intc11 0014h intc20 0016h intc21 0018h intc30 001ah intp4 001ch intp5 001eh intad 0020h intser 0022h intsr 0024h intcsi1 intst 0026h intcsi 0028h intser2 002ah intsr2 002ch intcsi2 intst2 002eh
46 m m m m m pd784020, 784021 9.3 context switching when an interrupt request is generated, or when the brkcs instruction is executed, an appropriate register bank is selected by the hardware. then, a branch to a vector address stored in that register bank occurs. at the same time, the contents of the current program counter (pc) and program status word (psw) are stacked in the register bank. the branch address must be within the range of 0 to ffffh. fig. 9-1 context switching caused by an interrupt request 9.4 macro service the macro service function enables data transfer between memory and special function registers (sfrs) without requiring the intervention of the cpu. the macro service controller accesses both memory and sfrs within the same transfer cycle to directly transfer data without having to perform data fetch. since the cpu status is neither saved nor restored, nor is data fetch performed, high-speed data transfer is possible. fig. 9-2 macro service psw pc19-16 0000b pc15-0 exchange save save 2 3 4 5 save 1 6 7 transfer (bits 8 to 11 of temporary register) register bank n (n = 0-7) temporary register ax bc r5 r4 r7 vp up r6 de h t u v wl switching between register banks (rbs0-rbs2 ? n) rss ? 0 ie ? 0 register bank (0-7) cpu sfr memory read write read write macro service controller internal bus
47 m m m m m pd784020, 784021 9.5 examples of macro service applications (1) serial interface transmission each time a macro service request (intst) is generated, the next transmission data is transferred from memory to txs. when data n (last byte) has been transferred to txs (that is, once the transmission data storage buffer becomes empty), a vectored interrupt request (intst) is generated. (2) serial interface reception each time a macro service request (intsr) is generated, reception data is transferred from rxb to memory. when data n (last byte) has been transferred to memory (that is, once the reception data storage buffer becomes full), a vectored interrupt request (intsr) is generated. transmission data storage buffer (memory) intst txs (sfr) txd data n data n-1 data 2 data 1 internal bus transmission shift register transmission control reception data storage buffer (memory) intsr rxb (sfr) rxd data n data n-1 data 2 data 1 internal bus reception buffer reception shift register reception control
48 m m m m m pd784020, 784021 (3) real-time output port intc10 and intc11 function as the output triggers for the real-time output ports. for these triggers, the macro service can simultaneously set the next output pattern and interval. therefore, intc10 and intc11 can be used to independently control two stepping motors. they can also be applied to pwm and dc motor control. each time a macro service request (intc10) is generated, a pattern and timing data are transferred to the buffer register (p0l) and compare register (cr10), respectively. when the contents of timer register 1 (tm1) and cr10 match, another intc10 is generated, and the p0l contents are transferred to the output latch. when tn (last byte) is transferred to cr10, a vectored interrupt request (intc10) is generated. for intc11, the same operation as that performed for intc10 is performed. match (sfr) intc10 p00-p03 (sfr) output pattern profile (memory) output timing profile (memory) p n p n? p 2 p 1 internal bus p0l output latch cr10 tm1 internal bus t n t n? t 2 t 1
49 m m m m m pd784020, 784021 10. local bus interface the local bus interface enables the connection of external memory and i/o devices (memory-mapped i/o). it supports a 1m-byte memory space. (see fig. 10-1 .) fig. 10-1 example of local bus interface 10.1 memory expansion by adding external memory, program memory or data memory can be expanded, 64k bytes at a time, to approximately 1m byte (three steps). data bus latch gate array for i/o expansion including centronics interface circuit, etc. rd wr refrq ad0-ad7 astb pseudo sram prom pd27c1001a pd784021 a16-a19 m m address bus data bus a8-a15 decoder kanji character generator pd24c1000 m
50 m m m m m pd784020, 784021 10.2 memory space the 1m-byte memory space is divided into eight spaces, each having a logical address. each of these spaces can be controlled using the programmable wait and pseudo-static ram refresh functions. fig. 10-2 memory space fffffh 80000h 7ffffh 40000h 3ffffh 20000h 1ffffh 10000h 0ffffh 0c000h 0bfffh 08000h 07fffh 04000h 03fffh 00000h 512k bytes 256k bytes 128k bytes 64k bytes 16k bytes 16k bytes 16k bytes 16k bytes
51 m m m m m pd784020, 784021 10.3 programmable wait when the memory space is divided into eight spaces, a wait state can be separately inserted for each memory space while the rd or wr signal is active. this prevents the overall system efficiency from being degraded even when memory devices having different access times are connected. in addition, an address wait function that extends the astb signal active period is provided to produce a longer address decode time. (this function is set for the entire space.) 10.4 pseudo-static ram refresh function refresh is performed as follows: ? pulse refresh : a bus cycle is inserted where a refresh pulse is output on the refrq pin at regular intervals. when the memory space is divided into eight, and a specified area is being accessed, refresh pulses can also be output on the refrq pin as the memory is being accessed. this can prevent the refresh cycle from suspending normal memory access. ? power-down self-refresh : in standby mode, a low-level signal is output on the refrq pin to maintain the contents of pseudo-static ram. 10.5 bus hold function a bus hold function is provided to facilitate connection to devices such as a dma controller. suppose that a bus hold request signal (hldrq) is received from an external bus master. in this case, upon the completion of the bus cycle being performed, the address bus, address/data bus, astb, rd, and wr pins are placed in the high-impedance state, and the bus hold acknowledge signal (hldak) is made active to release the bus for the external bus master. while the bus hold function is being used, the external wait and pseudo-static ram refresh functions are disabled.
52 m m m m m pd784020, 784021 11. standby function the standby function allows the power consumption of the chip to be reduced. the following standby modes are supported: ? halt mode : the cpu operation clock is stopped. by occassionally inserting the halt mode during normal operation, the overall average power consumption can be reduced. ? idle mode : the entire system is stopped, with the exception of the oscillator circuit. this mode consumes only very little more power than stop mode, but normal program operation can be restored in almost as little time as that required to restore normal program operation from halt mode. ? stop mode : the oscillator is stopped. all operations in the chip stop, such that only leakage current flows. these modes can be selected by software. a macro service can be initiated in halt mode. fig. 11-1 standby mode status transition notes 1. intp4 and intp5 are applied when not masked. 2. only when the interrupt request is not masked remark nmi is enabled only by external input. the watchdog timer cannot be used to release one of the standby modes (stop or idle mode). stop (standby) idle (standby) request for masked interrupt halt (standby) nmi, intp4, intp5 input note 1 set stop reset input set idle reset input nmi, intp4, intp5 input note 1 oscillation settling time elapses wait for oscillation settling program operation macro service request end of one operation end of macro service macro service set halt reset input interrupt request note 2 macro service request end of one operation
53 m m m m m pd784020, 784021 12. reset function applying a low-level signal to the reset pin initializes the internal hardware (reset status). when the reset input makes a low-to-high transition, the following data is loaded into the program counter (pc): ? eight low-order bits of the pc : contents of location at address 0000h ? intermediate eight bits of the pc : contents of location at address 0001h ? four high-order bits of the pc : 0 the pc contents are used as a branch destination address. program execution starts from that address. therefore, a reset start can be performed from an arbitrary address. the contents of each register can be set by software, as required. the reset input circuit contains a noise eliminator to prevent malfunctions caused by noise. this noise eliminator is an analog delay sampling circuit. fig. 12-1 accepting a reset for power-on reset, the reset signal must be held active until the oscillation settling time (approximately 40 ms) has elapsed. fig. 12-2 power-on reset reset (input) delay delay delay initialize pc execute instruction at reset start address internal reset signal start reset end reset oscillation settling time delay initialize pc execute instruction at reset start address reset (input) internal reset signal end reset v dd
54 m m m m m pd784020, 784021 13. instruction set (1) 8-bit instructions (the instructions enclosed in parentheses are implemented by a combination of operands, where a is described as r.) mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, shr, shl, ror4, rol4, dbnz, push, pop, movm, xchm, cmpme, cmpmne, cmpmnc, cmpmc, movbk, xchbk, cmpbke, cmpbkne, cmpbknc, cmpbkc, chkl, chkla table 13-1 instructions implemented by 8-bit addressing 2nd operand #byte a r saddr sfr !addr16 mem r3 [whl+] n none note 2 r' saddr' !!addr24 [saddrp] pswl [whlC] 1st operand [%saddrg] pswh a (mov) (mov) mov (mov) note 6 mov (mov) mov mov (mov) add note 1 (xch) xch (xch) note 6 (xch) (xch) xch (xch) (add) note 1 (add) note 1 (add) notes 1, 6 (add) note 1 add note 1 add note 1 (add) note 1 r mov (mov) mov mov mov mov ror note 3 mulu add note 1 (xch) xch xch xch xch divuw (add) note 1 add note 1 add note 1 add note 1 inc dec saddr mov (mov) note 6 mov mov inc add note 1 (add) note 1 add note 1 xch dec add note 1 dbnz sfr mov mov mov push add note 1 (add) note 1 add note 1 pop chkl chkla !addr16 mov (mov) mov !!addr24 add note 1 mem mov [saddrp] add note 1 [%saddrg] mem3 ror4 rol4 r3 mov mov pswl pswh b, c dbnz stbc, wdm mov [tde+] (mov) movbk note 5 [tdeC] (add) note 1 movm note 4 notes 1. addc, sub, subc, and, or, xor, and cmp are the same as add. 2. there is no second operand, or the second operand is not an operand address. 3. rol, rorc, rolc, shr, and shl are the same as ror. 4. xchm, cmpme, cmpmne, cmpmnc, and cmpmc are the same as movm. 5. xchbk, cmpbke, cmpbkne, cmpbknc, and cmpbkc are the same as movbk. 6. when saddr is saddr2 with this combination, an instruction with a short code exists.
55 m m m m m pd784020, 784021 (2) 16-bit instructions (the instructions enclosed in parentheses are implemented by a combination of operands, where ax is described as rp.) movw, xchw, addw, subw, cmpw, muluw, mulw, divux, incw, decw, shrw, shlw, push, pop, addwg, subwg, pushu, popu, movtblw, macw, macsw, sacw table 13-2 instructions implemented by 16-bit addressing 2nd operand #word ax rp saddrp strp !addr16 mem [whl+] byte n none note 2 rp' saddrp' !!addr24 [saddrp] 1st operand [%saddrg] ax (movw) (movw) (movw) (movw) note 3 movw (movw) movw (movw) addw note 1 (xchw) (xchw) (xchw) note 3 (xchw) xchw xchw (xchw) (add) note 1 (addw) note 1 (addw) notes 1,3 (addw) note 1 rp movw (movw) movw movw movw movw shrw mulw note 4 addw note 1 (xchw) xchw xchw xchw shlw incw (addw) note 1 addw note 1 addw note 1 addw note 1 decw saddrp movw (movw) note 3 movw movw incw addw note 1 (addw) note 1 addw note 1 xchw decw addw note 1 sfrp movw movw movw push addw note 1 (addw) note 1 addw note 1 pop !addr16 movw (movw) movw movtblw !!addr24 mem movw [saddrp] [%saddrg] psw push pop sp addwg subwg post push pop pushu popu [tde+] (movw) sacw byte macw macsw notes 1. subw and cmpw are the same as addw. 2. there is no second operand, or the second operand is not an operand address. 3. when saddrp is saddrp2 with this combination, an instruction with a short code exists. 4. muluw and divux are the same as mulw.
56 m m m m m pd784020, 784021 (3) 24-bit instructions (the instructions enclosed in parentheses are implemented by a combination of operands, where whl is described as rg.) movg, addg, subg, incg, decg, push, pop table 13-3 instructions implemented by 24-bit addressing 2nd operand #imm24 whl rg saddrg !!addr24 mem1 [%saddrg] sp none note 1st operand rg' whl (movg) (movg) (movg) (movg) (movg) movg movg movg (addg) (addg) (addg) addg (subg) (subg) (subg) subg rg movg (movg) movg movg movg incg addg (addg) addg decg subg (subg) subg push pop saddrg (movg) movg !!addr24 (movg) movg mem1 movg [%saddrg] movg sp movg movg incg decg note there is no second operand, or the second operand is not an operand address.
57 m m m m m pd784020, 784021 (4) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr, bfset table 13-4 bit manipulation instructions implemented by addressing 2nd operand cy saddr.bit sfr.bit /saddr.bit /sfr.bit none note a.bit x.bit /a.bit /x.bit pswl.bit pswh.bit /pswl.bit /pswh.bit mem2.bit /mem2.bit 1st operand !addr16.bit !!addr24.bit /!addr16.bit /!!addr24.bit cy mov1 and1 not1 and1 or1 set1 or1 clr1 xor1 saddr.bit mov1 not1 sfr.bit set1 a.bit clr1 x.bit bf pswl.bit bt pswh.bit btclr mem2.bit bfset !addr16.bit !!addr24.bit note there is no second operand, or the second operand is not an operand address.
58 m m m m m pd784020, 784021 (5) call/return instructions and branch instructions call, callf, callt, brk, ret, reti, retb, retcs, retcsb, brkcs, br, bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz table 13-5 call/return and branch instructions implemented by addressing instruction $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] rbn none address operand basic bc note call call call call call call call callf callf brkcs brk instruction br br br br br br br br ret retcs reti retcsb retb composite bf instruction bt btclr bfset dbnz note bnz, bne, bz, be, bnc, bnl, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, and bh are the same as bc. (6) other instructions adjba, adjbs, cvtbw, location, sel, not ei, di, swrs
59 m m m m m pd784020, 784021 14. electrical characteristics the electrical characteristics described in this chapter apply to the products which are improved versions of the m pd784020 and m pd784021 (other than k-rank products). for k-rank products yet to be improved (k-rank products), please consult with our sales offices. h parameter supply voltage input voltage output voltage low-level output current high-level output current a/d converter reference input voltage d/a converter reference input voltage operating ambient temperature storage temperature conditions each pin total of all output pins each pin total of all output pins symbol v dd av dd av ss v i v o i ol i oh av ref1 av ref2 av ref3 t a t stg rating C0.5 to +7.0 av ss to v dd + 0.5 C0.5 to +0.5 C0.5 to v dd + 0.5 C0.5 to v dd + 0.5 15 150 C10 C100 C0.5 to v dd + 0.3 C0.5 to v dd + 0.3 C0.5 to v dd + 0.3 C40 to +85 C65 to +150 unit v v v v v ma ma ma ma v v v c c absolute maximum ratings (t a = 25 c) caution absolute maximum ratings are rated values beyond which some physical damages may be caused to the product; if any of the parameters in the table above exceeds its rated value even for a moment, the quality of the product may deteriorate. be sure to use the product within the rated values.
60 m m m m m pd784020, 784021 operating conditions ? operating ambient temperature (t a ): C40 to +85 c ? rising and falling time (t r , t f ) (for pins not especially specified): 0 to 200 m s ? power supply voltage and clock cycle time: see fig. 14-1 . fig. 14-1 relationship between power supply voltage and clock cycle time capacitance (t a = 25 c, v dd = v ss = 0 v) parameter input capacitance output capacitance i/o capacitance unit pf pf pf max. 10 10 10 typ. min. symbol c i c o c io conditions f = 1 mhz 0 v on pins other than measured pins 10000 4000 1000 125 100 80 10 01234567 clock cycle time t cyk [ns] operation guarantee range power supply voltage [v]
61 m m m m m pd784020, 784021 oscillator characteristics (t a = C40 to +85 c, v dd = 4.5 to 5.5 v, v ss = 0 v) resonator ceramic resonator or crystal external clock recommended circuit min. 4 4 0 10 unit mhz mhz ns ns parameter oscillator frequency (f xx ) x1 input frequency (f x ) x1 input rising and falling times (t xr , t xf ) x1 input high-level and low- level widths (t wxh , t wxl ) max. 25 25 10 125 x1 x2 v ss c1 c2 x1 x2 hcmos inverter caution when using the system clock generator, run wires in the portion surrounded by dotted lines according to the following rules to avoid effects such as stray capacitance: ? minimize the wiring. ? never cause the wires to cross other signal lines. ? never cause the wires to run near a line carrying a large varying current. ? cause the grounding point of the capacitor of the oscillator circuit to have the same potential as v ss . never connect the capacitor to a ground pattern carrying a large current. ? never extract a signal from the oscillator.
62 m m m m m pd784020, 784021 oscillator characteristics (t a = C40 to +85 c, v dd = 2.7 to 5.5 v, v ss = 0 v) resonator ceramic resonator or crystal external clock recommended circuit min. 4 4 0 10 unit mhz mhz ns ns parameter oscillator frequency (f xx ) x1 input frequency (f x ) x1 input rising and falling times (t xr , t xf ) x1 input high-level and low- level widths (t wxh , t wxl ) max. 16 16 10 125 x1 x2 v ss c1 c2 x1 x2 hcmos inverter caution when using the system clock generator, run wires in the portion surrounded by dotted lines according to the following rules to avoid effects such as stray capacitance: ? minimize the wiring. ? never cause the wires to cross other signal lines. ? never cause the wires to run near a line carrying a large varying current. ? cause the grounding point of the capacitor of the oscillator circuit to have the same potential as v ss . never connect the capacitor to a ground pattern carrying a large current. ? never extract a signal from the oscillator.
63 m m m m m pd784020, 784021 dc characteristics (t a = C40 to +85 c, v dd = av dd = 2.7 to 5.5 v, v ss = av ss = 0 v) (1/2) notes 1. x1, x2, reset, p12/asck2/sck2, p13/rxd2/si2, p20/nmi, p21/intp0, p22/intp1, p23/intp2/ci, p24/intp3, p25/intp4/asck/sck1, p26/intp5, p27/si0, p30/rxd/si1, p32/sck0, p33/so0/sb0, and test 2. ad0 to ad7 and a8 to a15 3. p60/a16 to p63/a19, rd, wr, p66/wait/hldrq, and p67/refrq/hldak 4. p00 to p07 5. p10 to p17 parameter low-level input voltage high-level input voltage low-level output voltage high-level output voltage x1 low-level input current x1 high-level input current symbol v il1 v il2 v il3 v ih1 v ih2 v ih3 v ol1 v ol2 v oh1 v oh2 i il i ih conditions pins other than those described in notes 1, 2, 3, and 4 pins described in notes 1, 2, 3, and 4 v dd = +5.0 v 10 % pins described in notes 2, 3, and 4 pins other than those described in note 1 pins described in note 1 v dd = +5.0 v 10 % pins described in notes 2, 3, and 4 i ol = 2 ma v dd = +5.0 v 10 % i ol = 8 ma pins described in notes 2 and 5 i oh = C2 ma v dd = +5.0 v 10 % i oh = C5 ma pins described in note 4 0 v v i v il2 v ih2 v i v dd unit v v v v v v v v v v m a m a min. C0.3 C0.3 C0.3 0.7v dd 0.8v dd 2.2 v dd C 1.0 2.0 typ. max. 0.3v dd 0.2v dd +0.8 v dd + 0.3 v dd + 0.3 v dd + 0.3 0.4 1.0 C30 +30
64 m m m m m pd784020, 784021 dc characteristics (t a = C40 to +85 c, v dd = av dd = 2.7 to 5.5 v, v ss = av ss = 0 v) (2/2) parameter input leakage current output leakage current v dd supply current pull-up resistance symbol i li i lo i dd1 i dd2 i dd3 r l unit m a m a m a ma ma ma ma ma ma k w k w min. 15 15 typ. 40 12 22 8 max. 10 3 10 60 25 30 12 12 8 100 160 conditions 0 v v i v dd except for the x1 pin when extc = 0 0 v v i v dd analog input pins 0 v v o v dd operating mode f xx = 25 mhz f xx = 16 mhz v dd = 2.7 to 5.5 v halt mode f xx = 25 mhz f xx = 16 mhz v dd = 2.7 to 5.5 v idle mode f xx = 25 mhz (extc = 0) f xx = 16 mhz v dd = 2.7 to 5.5 v v i = 0 v v dd = +5.0 v 10 % v i = 0 v v dd = 2.7 to 4.5 v
65 m m m m m pd784020, 784021 ac characteristics (t a = C40 to +85 c, v dd = av dd = 2.7 to 5.5 v, v ss = av ss = 0 v) (1) read/write operation (1/2) remark t: t cyk (system clock cycle time) a: 1 when address wait is applied, 0 in other cases n: number of wait cycles (n ? 0) parameter address setup time astb high-level width address hold time (referred to astb ? ) address hold time (referred to rd ? ) address ? rd ? delay time address float time (referred to rd ? ) address ? data input time astb ? ? data input time rd ? ? data input time astb ? ? rd ? delay time data hold time (referred to rd ? ) rd ? ? address active time rd ? ? astb ? delay time rd low-level width address hold time (referred to wr ? ) address ? wr ? delay time astb ? ? data output delay time astb ? ? data output time astb ? ? wr ? output delay time symbol t sast t wsth t hstla t hra t dar t fra t daid t dstid t drid t dstr t hrid t dra t drst t wrl t hwa t daw t dstod t dwod t dstw unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. (0.5 + a) t C 11 (0.5 + a) t C 15 (0.5 + a) t C 17 (0.5 + a) t C 40 0.5t C 24 0.5t C 34 0.5t C 14 (1 + a) t C 5 (1 + a) t C 10 0.5t C 9 0 0.5t C 2 0.5t C 12 1.5t C 2 1.5t C 12 0.5t C 9 (1.5 + n) t C 30 (1.5 + n) t C 40 0.5t C 14 (1 + a) t C 5 (1 + a) t C 10 0.5t C 9 max. 0 (2.5 + a + n) t C 37 (2.5 + a + n) t C 52 (2 + n) t C 40 (2 + n) t C 60 (1.5 + n) t C 50 (1.5 + n) t C 70 0.5t + 15 0.5t + 20 0.5t C 11 conditions v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % upon program v dd = +5.0 v 10 % read upon data read v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 %
66 m m m m m pd784020, 784021 (1) read/write operation (2/2) note the hold time includes the time for holding v oh1 and v ol1 on the load conditions of c l = 50 pf and r l = 4.7 k w . remark t: t cyk (system clock cycle time) n: number of wait cycles (n ? 0) (2) bus hold timing remark t: t cyk (system clock cycle time) a: 1 when address wait is applied, 0 in other cases n: number of wait cycles (n ? 0) parameter data setup time (referred to wr ? ) data hold time (referred to wr ? ) note wr ? ? astb ? delay time wr low-level width symbol t sodw t hwod t dwst t wwl unit ns ns ns ns ns ns ns min. (1.5 + n) t C 30 (1.5 + n) t C 40 0.5t C 5 0.5t C 14 0.5t C 9 (1.5 + n) t C 30 (1.5 + n) t C 40 max. conditions v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % parameter hldrq ? ? float delay time hldrq ? ? hldak ? delay time float ? hldak ? delay time hldrq ? ? hldak ? delay time hldak ? ? active delay time symbol t fhqc t dhqhhah t dcfha t dhqlhal t dhac unit ns ns ns ns ns ns ns ns min. 1t C 20 1t C 30 max. (6 + a + n) t + 50 (7 + a + n) t + 30 (7 + a + n) t + 40 1t + 30 2t + 40 2t + 60 conditions v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 %
67 m m m m m pd784020, 784021 (3) external wait timing remark t: t cyk (system clock cycle time) a: 1 when address wait is applied, 0 in other cases n: number of wait cycles (n ? 0) (4) refresh timing remark t: t cyk (system clock cycle time) parameter address ? wait ? input time astb ? ? wait ? input time astb ? ? wait hold time astb ? ? wait ? delay time rd ? ? wait ? input time rd ? ? wait ? hold time rd ? ? wait ? delay time wait ? ? data input time wait ? ? wr ? delay time wait ? ? rd ? delay time wr ? ? wait ? input time wr ? ? wait hold time wr ? ? wait ? delay time symbol t dawt t dstwt t hstwth t dstwth t drwtl t hrwt t drwth t dwtid t dwtw t dwtr t dwwtl t hwwt t dwwth unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. (0.5 + n) t + 5 (0.5 + n) t + 10 nt + 5 nt + 10 0.5t 0.5t nt + 5 nt + 10 max. (2 + a) t C 40 (2 + a) t C 60 1.5t C 40 1.5t C 60 (1.5 + n) t C 40 (1.5 + n) t C 60 t C 50 t C 70 (1 + n) t C 40 (1 + n) t C 60 0.5t C 5 0.5t C 10 t C 50 t C 75 (1 + n) t C 40 (1 + n) t C 60 conditions v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % parameter random read/write cycle time refrq low-level pulse width astb ? ? refrq delay time rd ? ? refrq delay time wr ? ? refrq delay time refrq ? ? astb delay time refrq high-level pulse width symbol t rc t wrfql t dstrfq t drrfq t dwrfq t drfqst t wrfqh unit ns ns ns ns ns ns ns ns ns min. 3t 1.5t C 25 1.5t C 30 0.5t C 9 1.5t C 9 1.5t C 9 0.5t C 9 1.5t C 25 1.5t C 30 max. conditions v dd = +5.0 v 10 % v dd = +5.0 v 10 %
68 m m m m m pd784020, 784021 serial operation (csi) remarks 1. the values listed in the above table are obtained when f xx = 25 mhz and c l = 100 pf. 2. t cyx = 1/f xx 3. t: serial clock frequency specified using software. the minimum value is 16/f xx . parameter serial clock cycle time (sck0) serial clock low-level width (sck0) serial clock high-level width (sck0) si0, sb0 setup time (referred to sck0 ? ) si0, sb0 hold time (referred to sck0 ? ) so0, sb0 output delay time (referred to sck0 ? ) so0, sb0 output hold time (referred to sck0 ? ) sb0 high hold time (referred to sck0 ? ) sb0 low setup time (referred to sck0 ? ) sb0 low-level width sb0 high-level width symbol t cysk0 t wskl0 t wskh0 t sssk0 t hssk0 t dsbsk1 t dsbsk2 t hsbsk1 t hsbsk2 t ssbsk t wsbl t wsbh unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns t cyx t cyx t cyx t cyx min. 500 1000 t 210 460 0.5t C 40 210 460 0.5t C 40 80 80 0 0 0.5t cysk0 C 40 4 4 4 4 max. 150 400 conditions input v dd = +5.0 v 10 % output input v dd = +5.0 v 10 % output input v dd = +5.0 v 10 % output cmos push-pull output (three-wire serial i/o mode) open-drain output (sbi mode), r l = 1 k w during data transfer sbi mode
69 m m m m m pd784020, 784021 serial operation (ioe1, ioe2) remarks 1. the values listed in the above table are obtained when c l = 100 pf. 2. t: serial clock frequency specified using software. the minimum value is 16/f xx . serial operation (uart, uart2) unit ns ns ns ns ns ns ns ns ns ns ns ns ns min. 250 500 t 85 210 0.5t C 40 85 210 0.5t C 40 40 40 0 0.5t cysk1 C 40 max. 50 conditions input v dd = +5.0 v 10 % output internal clock divided by 16 input v dd = +5.0 v 10 % output internal clock divided by 16 input v dd = +5.0 v 10 % output internal clock divided by 16 during data transfer symbol t cysk1 t wskl1 t wskh1 t sssk1 t hssk1 t dsosk t hsosk parameter serial clock cycle time (sck1, sck2) serial clock low-level width (sck1, sck2) serial clock high-level width (sck1, sck2) si1, si2 setup time (referred to sck1, sck2 ? ) si1, si2 hold time (referred to sck1, sck2 ? ) so1, so2 output delay time (referred to sck1, sck2 ? ) so1, so2 output hold time (referred to sck1, sck2 ? ) parameter asck clock input cycle time asck clock low-level width asck clock high-level width symbol t cyask t waskl t waskh unit ns ns ns ns ns ns min. 125 250 52.5 85 52.5 85 max. conditions v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 %
70 m m m m m pd784020, 784021 other operations remark t cysmp : sampling clock specified using software t cycpu : cpu operating clock specified using cpu software a/d converter characteristics (t a = C40 to +85 c, v dd = av dd = 3.4 to 5.5 v, +3.4 v av ref1 av dd , v ss = av ss = 0 v) note quantization error is excluded. the error is represented in percent with respect to a full-scale value. remark t cyk : system clock cycle time parameter nmi low-level width nmi high-level width intp0 low-level width intp0 high-level width intp1-intp3 and ci low- level width intp1-intp3 and ci high- level width intp4 and intp5 low-level width intp4 and intp5 high-level width reset low-level width reset high-level width symbol t wnil t wnih t wit0l t wit0h t wit1l t wit1h t wit2l t wit2h t wrsl t wrsh unit m s m s ns ns ns ns m s m s m s m s min. 10 10 3t cysmp + 10 3t cysmp + 10 3t cycpu + 10 3t cycpu + 10 10 10 10 10 max. conditions parameter resolution total error note linearity calibration note quantization error conversion time sampling time analog input voltage analog input impedance av ref1 current av dd supply current symbol t conv t samp v ian r an ai ref1 ai dd1 ai dd2 unit bit % % % % lsb t cyk t cyk t cyk t cyk v m w ma ma m a min. 8 120 180 24 36 C0.3 typ. 1000 0.5 2.0 max. 1.2 1.0 1.0 0.6 1/2 av ref1 + 0.3 1.5 5.0 20 conditions v dd = av dd = +5.0 v 10 % +3.4 v av ref1 av dd +2.7 v v dd = av dd +3.3 v +2.5 v av ref1 av dd t cyk 500 ns, fr = 1 t cyk 500 ns, fr = 0 t cyk 500 ns, fr = 1 t cyk 500 ns, fr = 0 f xx = 25 mhz stop mode, cs = 0
71 m m m m m pd784020, 784021 d/a converter characteristics (t a = C40 to +85 c, av ref2 = v dd = av dd = 2.7 to 5.5 v, av ref3 = v ss = av ss = 0 v) note dacs0, dacs1 = 7fh parameter resolution total error note settling time output resistance analog reference voltage reference supply input current symbol r o av ref2 av ref3 ai ref2 ai ref3 unit bit % % % % % % % % m s k w v v ma ma typ. 20 max. 0.4 0.6 0.6 0.8 0.6 0.8 0.8 1.0 10 v dd 0.25v dd 5 0 conditions load condition: v dd = 4.5 to 5.5 v 4 m w , 30 pf v dd = 4.5 to 5.5 v av ref2 = 0.75v dd av ref3 = 0.25v dd av ref2 = 0.75v dd av ref3 = 0.25v dd load condition: v dd = 4.5 to 5.5 v 2 m w , 30 pf v dd = 4.5 to 5.5 v av ref2 = 0.75v dd av ref3 = 0.25v dd av ref2 = 0.75v dd av ref3 = 0.25v dd load condition: 2 m w , 30 pf note min. 8 0.75v dd 0 0 C5
72 m m m m m pd784020, 784021 data retention characteristics (t a = C40 to +85 c) notes 1. when the input voltage for the pins described in note 2 satisfies the v il and v ih conditions in the above table 2. pins reset, p20/nmi, p21/intp0, p22/intp1, p23/intp2/ci, p24/intp3, p25/intp4/asck/sck1, p26/intp5, p27/si0, p32/sck0, and p33/so0/sb0 ac timing test points parameter data retention voltage data retention current v dd rising time v dd falling time v dd retention time (referred to stop mode setting) stop release signal input time oscillation settling time low-level input voltage high-level input voltage symbol v dddr i dddr t rvd t fvd t hvd t drel t wait v il v ih unit v m a m a m s m s ms ms ms ms v v min. 2.5 200 200 0 0 30 5 0 0.9v dddr typ. 10 2 max. 5.5 50 10 0.1v dddr v dddr conditions stop mode v dddr = 2.5 to 5.5 v note 1 v dddr = 2.5 v note 1 crystal ceramic resonator specified pins note 2 v dd ?1 v 0.45 v 0.8v dd or 2.2 v 0.8 v test points 0.8v dd or 2.2 v 0.8 v
73 m m m m m pd784020, 784021 timing waveform (1) read operation (2) write operation t wsth t dstid t hstla t sast astb a8-a19 ad0-ad7 rd t daid t dstr t fra t dar t drid t wrl t drst t hra t hrid t dra astb a8-a19 ad0-ad7 wr t wsth t dstod t hstla t sast t dstw t daw t dwod t wwl t dwst t hwa t hwod t dsodw
74 m m m m m pd784020, 784021 hold timing external wait signal input timing (1) read operation (2) write operation astb, a8-a19, ad0-ad7, rd, wr hldrq hldak t fhqc t dcfha t dhqhhah t dhqlhal t dhac astb a8-a19 ad0-ad7 rd wait t dstwth t hstwth t dstwt t dawt t dwtid t dwtr t drwtl t hrwt t drwth t dstwth t hstwth t dstwt t dawt t dwtw t dwwtl t hwwt t dwwth astb a8-a19 ad0-ad7 wr wait
75 m m m m m pd784020, 784021 timing waveform for refresh (1) random read/write cycle (2) when a refresh is performed simultaneously with a memory access (3) refresh after reading (4) refresh after writing astb wr rd t rc t rc t rc t rc t rc astb rd, wr refrq t dstrfq t wrfql t wrfqh t drfqst astb rd refrq t drfqst t drrfq t wrfql t drfqst t dwrfq t wrfql astb wr refrq
76 m m m m m pd784020, 784021 serial operation (csi) (1) three-wire serial i/o mode (2) sbi mode y bus release signal transfer y command signal transfer sck si so t wskl0 t wskh0 t sssk0 t hssk0 t dsbsk1 input data output data t hsbsk1 t cysk0 sck sb0 t hsbsk2 t wsbl t wsbh t ssbsk sck sb0 t hsbsk1 t sssk0 input/output data t hsbsk2 t ssbsk t wskl0 t wskh0 t cysk0 t hssk0 t dsbsk2
77 m m m m m pd784020, 784021 serial operation (ioe1, ioe2) serial operation (uart, uart2) sck si so input data output data t wskl1 t wskh1 t dsosk t sssk1 t hssk1 t hsosk t cysk1 asck, asck2 t waskh t waskl 0.8v dd 0.8 v t cyask
78 m m m m m pd784020, 784021 interrupt input timing reset input timing nmi intp0 ci, intp1-intp3 intp4, intp5 t wnih t wnil 0.8v dd 0.8 v t wit0h t wit0l 0.8v dd 0.8 v t wit1h t wit1l 0.8v dd 0.8 v t wit2h t wit2l 0.8v dd 0.8 v reset t wrsh t wrsl 0.8v dd 0.8 v
79 m m m m m pd784020, 784021 external clock timing data retention timing x1 0.8v dd 0.8 v t xf t xr t wxl t cyx t wxh v dd t hvd t fvd set stop mode. v dddr t rvd t drel 0.8v dd 0.8 v 0.8v dd 0.8 v 0.8v dd 0.8 v reset nmi (released by a falling edge) nmi (released by a rising edge) t wait
80 m m m m m pd784020, 784021 15. package drawings remark the shape and material of the es version are the same as those of the corresponding mass-produced products. 80 pin plastic qfp (14 14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. l 0.8?.2 0.031 +0.009 ?.008 m 0.15 0.006 n 0.10 0.004 p 2.7 0.106 a 17.2?.4 0.677?.016 b 14.0?.2 0.551 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 d 17.2?.4 0.677?.016 f 0.825 0.032 g 0.825 0.032 h 0.30?.10 0.012 +0.004 ?.005 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) q 0.1?.1 0.004?.004 r5 ? 5 ? +0.10 ?.05 +0.004 ?.003 m m l k j h q p n r detail of lead end i g k 1.6?.2 0.063?.008 60 61 40 80 1 21 20 41 a b cd f s s80gc-65-3b9-4 s 3.0 max. 0.119 max.
81 m m m m m pd784020, 784021 80 pin plastic tqfp (fine pitch) ( 12) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 14.0?.2 0.551 +0.009 ?.008 b 12.0?.2 0.472 +0.009 ?.008 c 12.0?.2 0.472 +0.009 ?.008 d 14.0?.2 0.551 +0.009 ?.008 f g 1.25 1.25 0.049 0.049 h 0.22 0.009?.002 p80gk-50-be9-4 s 1.27 max. 0.050 max. k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 m 0.145 0.006?.002 n 0.10 0.004 p 1.05 0.041 q 0.05?.05 0.002?.002 r 55 55 +0.05 ?.04 +0.055 ?.045 b c d j h i g f p n l k m q r detail of lead end m 61 60 41 40 21 20 1 80 remark the shape and material of the es version are the same as those of the corresponding mass-produced products. h
82 m m m m m pd784020, 784021 16. recommended soldering conditions the conditions listed below shall be met when soldering the m pd784021. for details of the recommended soldering conditions, refer to our document smd surface mount technology manual (c10535e) . please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. table 16-1 soldering conditions for surface-mount devices (1) m m m m m pd784020gc-3b9 : 80-pin plastic qfp (14 14 mm) m m m m m pd784021gc-3b9 : 80-pin plastic qfp (14 14 mm) (2) m m m m m pd784021gk-be9: 80-pin plastic tqfp (fine pitch) (12 12 mm) note exposure limit before soldering after dry-pack package is opened. storage conditions: temperature of 25 ?c and maximum relative humidity at 65 % or less caution do not apply more than a single process at once, except for partial heating method. h soldering conditions peak packages surface temperature: 235 ?c reflow time: 30 seconds or less (at 210 ?c or more) maximum allowable number of reflow processes: 3 peak packages surface temperature: 215 ?c reflow time: 40 seconds or less (at 210 ?c or more) maximum allowable number of reflow processes: 3 solder temperature: 260 ?c or less flow time: 10 seconds or less number of flow process: 1 preheating temperature: 120 ?c max. (measured on the package surface) terminal temperature: 300 ?c or less flow time: 3 seconds or less (for each side of device) symbol ir35-00-3 vp15-00-3 ws60-00-1 C soldering process infrared ray reflow vps wave soldering partial heating method soldering conditions peak packages surface temperature: 235 ?c reflow time: 30 seconds or less (at 210 ?c or more) maximum allowable number of reflow processes: 2 exposure limit note : 7 days (10 hours of pre-baking is required at 125 ?c afterward.) non-heat resistant trays, such as magazine and taping trays, cannot be baked before unpacking. peak packages surface temperature: 215 ?c reflow time: 40 seconds or less (at 200 ?c or more) maximum allowable number of reflow processes: 2 exposure limit note : 7 days (10 hours of pre-baking is required at 125 ?c afterward.) non-heat resistant trays, such as magazine and taping trays, cannot be baked before unpacking. terminal temperature: 300 ?c or less flow time: 3 seconds or less (for each side of device) symbol ir35-107-2 vp15-107-2 C soldering process infrared ray reflow vps partial heating method
83 m m m m m pd784020, 784021 appendix a development tools the following development tools are available for system development using the m pd784021. language processing software ra78k4 note 1 assembler package for all 78k/iv series models cc78k4 note 1 c compiler package for all 78k/iv series models cc78k4-l note 1 c compiler library source file for all 78k/iv series models prom write tools pg-1500 prom programmer pa-78p4026gc programmer adaptor, connects to pg-1500 pa-78p4038gk pa-78p4026kk pg-1500 controller note 2 control program for pg-1500 debugging tools ie-784000-r in-circuit emulator for all m pd784026 sub-series models ie-784000-r-bk break board for all 78k/iv series models ie-784026-r-em1 emulation board for evaluating m pd784026 sub-series models ie-784000-r-em ie-70000-98-if-b interface adapter when the pc-9800 series computer (other than a notebook) is used as the host machine ie-70000-98n-if interface adapter and cable when a pc-9800 series notebook is used as the host machine ie-70000-pc-if-b interface adapter when the ibm pc/at tm is used as the host machine ie-78000-r-sv3 interface adapter and cable when the ews is used as the host machine ep-78230gc-r emulation probe for 80-pin plastic qfp (14 14 mm) for all m pd784026 sub-series ep-78054gk-r emulation probe for 80-pin plastic tqfp (fine pitch) (12 12 mm) for all m pd784021 ev-9200gc-80 socket for mounting on target system board made for 80-pin plastic qfp (14 14 mm) ev-9500gk-80 adapter for mounting on target system board made for 80-pin plastic tqfp (fine pitch) (12 12 mm) ev-9900 tool used to remove the m pd78p4026kk-t from the ev-9200gc-80 sm78k4 note 3 system simulator for all 78k/iv series models id78k4 note 3 integrated debugger for ie-784000-r df784026 note 4 device file for all m pd784026 sub-series models real-time os rx78k/iv note 4 real-time os for 78k/iv series models mx78k4 note 2 os for all 78k/iv series models remark the ra78k4, cc78k4, sm78k4, and id78k4 are used with the df784026.
84 m m m m m pd784020, 784021 notes 1. ? based on pc-9800 series (ms-dos tm ) ? based on ibm pc/at and compatibles (pc dos tm , windows tm , ms-dos, and ibm dos tm ) ? based on hp9000 series 700 tm (hp-ux tm ) ? based on sparcstation tm (sunos tm ) ? based on news tm (news-os tm ) 2. ? based on pc-9800 series (ms-dos) ? based on ibm pc/at and compatibles (pc dos, windows, ms-dos, and ibm dos) 3. ? based on pc-9800 series (ms-dos + windows) ? based on ibm pc/at and compatibles (pc dos, windows, ms-dos, and ibm dos) ? based on hp9000 series 700 (hp-ux) ? based on sparcstation (sunos) 4. ? based on pc-9800 series (ms-dos) ? based on ibm pc/at and compatibles (pc dos, windows, ms-dos, and ibm dos) ? based on hp9000 series 700 (hp-ux) ? based on sparcstation (sunos)
85 m m m m m pd784020, 784021 appendix b related documents documents related to devices document name document no. japanese english m pd784020, 784021 data sheet u11514j this manual m pd784025, 784026 data sheet to be released soon ip-3230 m pd78p4026 data sheet to be released soon ip3231 m pd784026 sub-series user's manual, hardware u10898j u10898e m pd784026 sub-series special function registers u10593j m pd784026 sub-series application note, hardware basic u10573j 78k/iv series user's manual, instruction u10905j ieu-1386 78k/iv series instruction summary sheet u10594j 78k/iv series instruction set u10595j 78k/iv series application note, software basic u10095j documents related to development tools (users manual) document name document no. japanese english ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 cc78k series library source file eeu-777 pg-1500 prom programmer eeu-651 eeu-1335 pg-1500 controller pc-9800 series (ms-dos) base eeu-704 eeu-1291 pg-1500 controller ibm pc series (pc dos) base eeu-5008 u10540e ie-784000-r eeu-5004 eeu-1534 ie-784026-r-em1 eeu-5017 eeu-1528 ep-78230 eeu-985 eeu-1515 ep-78054gk-r eeu-932 eeu-1468 sm78k4 system simulator windows base reference u10093j u10093e sm78k series system simulator external parts user open u10092j u10092e interface specifications id78k4 integrated debugger reference u10440j u10440e caution the above documents may be revised without notice. use the latest versions when you design application systems.
86 m m m m m pd784020, 784021 documents related to software to be incorporated into the product (users manual) document name document no. japanese english 78k/iv series real-time os basic u10603j installation u10604j debugger u10364j os for 78k/iv series mx78k4 to be created other documents document name document no. japanese english ic package manual c10943x smd surface mount technology manual c10535j c10535e quality grades on nec semiconductor device iei-620 iei-1209 nec semiconductor device reliability/quality control system c10983j c10983e electrostatic discharge (esd) test mem-539 guide to quality assurance for semiconductor device mei-603 mei-1202 guide for products related to micro-computer: other companies mei-604 caution the above documents may be revised without notice. use the latest versions when you design application systems.
87 m m m m m pd784020, 784021 [memo]
88 m m m m m pd784020, 784021 ms-dos and windows are trademarks of microsoft corporation. ibm dos, pc/at, and pc dos are trademarks of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. cautions on cmos devices countermeasures against static electricity for all moss caution when handling mos devices, take care so that they are not electrostatically charged. strong static electricity may cause dielectric breakdown in gates. when transporting or storing mos devices, use conductive trays, magazine cases, shock absorbers, or metal cases that nec uses for packaging and shipping. be sure to ground mos devices during assembling. do not allow mos devices to stand on plastic plates or do not touch pins. also handle boards on which mos devices are mounted in the same way. cmos-specific handling of unused input pins caution hold cmos devices at a fixed input level. unlike bipolar or nmos devices, if a cmos device is operated with no input, an intermediate- level input may be caused by noise. this allows current to flow in the cmos device, resulting in a malfunction. use a pull-up or pull-down resistor to hold a fixed input level. since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the v dd or gnd pin through a resistor. if handling of unused pins is documented, follow the instructions in the document. statuses of all mos devices at initialization caution the initial status of a mos device is unpredictable when power is turned on. since characteristics of a mos device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. nec has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. however, nec assures operation after reset and items for mode setting if they are defined. when you turn on a device having a reset function, be sure to reset the device first.
89 m m m m m pd784020, 784021 nec electronics inc. (u.s.) mountain view, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby sweden tel: 8-63 80 820 fax: 8-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 3
90 m m m m m pd784020, 784021 some related documents may be preliminary versions. note that, however, what documents are preliminary is not indicated in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written? consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this? document.? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual? property rights of third parties by or arising from use of a device described herein or any other liability arising? from use of such device. no license, either express, implied or otherwise, is granted under any patents,? copyrights or other intellectual property rights of nec corporation or others.? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices,? the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or? property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety? measures in its design, such as redundancy, fire-containment, and anti-failure features.? nec devices are classified into the following three quality grades:? "standard", "special", and "specific". the specific quality grade applies only to devices developed based on? a customer designated "quality assurance program" for a specific application. the recommended applications? of a device depend on its quality grade, as indicated below. customers must check the quality grade of each? device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment,? audio and visual equipment, home electronic appliances, machine tools, personal electronic? equipment and industrial robots? special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster? systems, anti-crime systems, safety equipment and medical equipment (not specifically designed? for life support)? specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life? support systems or medical equipment for life support, etc.? the quality grade of nec devices in "standard" unless otherwise specified in nec's data sheets or data books.? if customers intend to use nec devices for applications other than those specified for standard quality grade,? they should contact nec sales representative in advance.? anti-radioactive design is not implemented in this product. m4 94. 11

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